home
***
CD-ROM
|
disk
|
FTP
|
other
***
search
/
Languguage OS 2
/
Languguage OS II Version 10-94 (Knowledge Media)(1994).ISO
/
language
/
embedded
/
mcu
/
hc05iic.arc
/
C4C8REG.S
next >
Wrap
Text File
|
1990-04-26
|
9KB
|
261 lines
*********************************************************************
* 68HC05C4/C8 Assembly Language Equates
* File Name: C4C8REG.S
*
* This file contains assembly language equates defining the internal
* peripherals of the 68HC05C4 and C8 mask ROM microcontrollers.
* For the 68HC705C8 EPROM/OTP Device, use the file '705C8REG.S'
*
* Scott Howard, 1989
*
* Although this file has been carefully reviewed and is
* believed to be reliable, Motorola does not assume any
* liability arising out of its use.
*
* To use this file, either use an INCLUDE statement (pasm05)
* or just merge (Freeware AS5.EXE) this file into your source
* code file. Consult your assembler's user's manual for the
* details specific to your situation. Reference the code
* segment example below for usage ideas.
*
* INCLUDE C4C8REG.S
* START CLR PORTA
* LDX PORTB
* CLR DDRC
* BSET TIE,SCCR2
* BCLR PA1,PORTA
*
* Because the bit set/clear/test instructions on the HC05 specify a bit
* position rather than a bit mask, there are two labels representing each
* bit position of an I/O register. The the label without a proceeding
* underscore character is defined to represent the bit position in the
* byte, while the label beginning with the period character (.) is
* defined to represent the bit mask value. For example, the Transmit
* Interrupt Enable (TIE) bit in the SCI register SCCR2 is defined both as
* 'TIE' (the label used in bit set/clear/branch instructions) and '.TIE'
* (used for the mask value). These two labels would be used as follows:
*
* LDA #.TIE+.RIE initialize all bits of location SCCR2
* STA SCCR2
* BSET TIE,SCCR2 set bit 7 of location SCCR2
*
*********************************************************************
PAGE
* General Purpose Parallel I/O
PORTA EQU $0 Port A Data Register
PA0 EQU 0
PA1 EQU 1
PA2 EQU 2
PA3 EQU 3
PA4 EQU 4
PA5 EQU 5
PA6 EQU 6
PA7 EQU 7
.PA0 EQU 1
.PA1 EQU 2
.PA2 EQU 4
.PA3 EQU 8
.PA4 EQU $10
.PA5 EQU $20
.PA6 EQU $40
.PA7 EQU $80
PORTB EQU $1 Port B Data Register
PB0 EQU 0
PB1 EQU 1
PB2 EQU 2
PB3 EQU 3
PB4 EQU 4
PB5 EQU 5
PB6 EQU 6
PB7 EQU 7
.PB0 EQU 1
.PB1 EQU 2
.PB2 EQU 4
.PB3 EQU 8
.PB4 EQU $10
.PB5 EQU $20
.PB6 EQU $40
.PB7 EQU $80
PORTC EQU $2 Port C Data Register
PC0 EQU 0
PC1 EQU 1
PC2 EQU 2
PC3 EQU 3
PC4 EQU 4
PC5 EQU 5
PC6 EQU 6
PC7 EQU 7
.PC0 EQU 1
.PC1 EQU 2
.PC2 EQU 4
.PC3 EQU 8
.PC4 EQU $10
.PC5 EQU $20
.PC6 EQU $40
.PC7 EQU $80
PORTD EQU $3 Port C Data Register
PD0 EQU 0
PD1 EQU 1
PD2 EQU 2
PD3 EQU 3
PD4 EQU 4
PD5 EQU 5
PD7 EQU 7
.PD0 EQU 1
.PD1 EQU 2
.PD2 EQU 4
.PD3 EQU 8
.PD4 EQU $10
.PD5 EQU $20
.PD7 EQU $80
DDRA EQU $4 Port A Data Direction Register
DDRB EQU $5 Port B Data Direction Register
DDRC EQU $6 Port C Data Direction Register
PAGE
* Serial Peripheral Interface (SPI)
SPCR EQU $A Serial Peripheral Control Register
SPR0 EQU 0 SPI Clock Divide Ratio
SPR1 EQU 1 SPI Clock Divide Ratio
CPHA EQU 2 Clock Phase Bit
CPOL EQU 3 Clock Polarity Bit
MSTR EQU 4 1 = Master Mode
SPE EQU 6 1 = Enable SPI Subsystem
SPIE EQU 7 SPI Interrupt Enable
.SPR0 EQU 1 SPI Clock Divide Ratio
.SPR1 EQU 2 SPI Clock Divide Ratio
.CPHA EQU 4 Clock Phase Bit
.CPOL EQU 8 Clock Polarity Bit
.MSTR EQU $10 1 = Master Mode
.SPE EQU $40 1 = Enable SPI Subsystem
.SPIE EQU $80 SPI Interrupt Enable
SPSR EQU $B Serial Peripheral Status Register
MODF EQU 4 Mode Fault Flag
WCOL EQU 6 Write Collision Flag
SPIF EQU 7 SPI Interrupt Flag
.MODF EQU $10 Mode Fault Flag
.WCOL EQU $40 Write Collision Flag
.SPIF EQU $80 SPI Interrupt Flag
SPDR EQU $C Serial Peripheral Data Register
* Serial Communications Interface (SCI)
BAUD EQU $D SCI Baud Rate Register
SCR0 EQU 0 Divide Select 0
SCR1 EQU 1 Divide Select 1
SCR2 EQU 2 Divide Select 2
SCP0 EQU 4 Prescale Select 0
SCP1 EQU 5 Prescale Select 1
.SCR0 EQU 1 Divide Select 0
.SCR1 EQU 2 Divide Select 1
.SCR2 EQU 4 Divide Select 2
.SCP0 EQU $10 Prescale Select 0
.SCP1 EQU $20 Prescale Select 1
SCCR1 EQU $E SCI Control Register 1
WAKE EQU 3 Wakeup Method Select
M EQU 4 Select 8 or 9 bits Word Length
T8 EQU 6 Transmit 8th Data Bit
R8 EQU 7 Received 8th Data Bit
.WAKE EQU 8 Wakeup Method Select
.M EQU $10 Select 8 or 9 bits Word Length
.T8 EQU $40 Transmit 8th Data Bit
.R8 EQU $80 Received 8th Data Bit
SCCR2 EQU $F SCI Control Register 2
SBK EQU 0 Send Break
RWU EQU 1 Receiver Wake Up
RE EQU 2 Receiver Enable
TE EQU 3 Transmitter Enable
ILIE EQU 4 Idle Line Interrupt Enable
RIE EQU 5 Receive Interrupt Enable
TCIE EQU 6 Transmision Complete Interrupt Enable
TIE EQU 7 Transmission Interrupt Enable
.SBK EQU 1 Send Break
.RWU EQU 2 Receiver Wake Up
.RE EQU 4 Receiver Enable
.TE EQU 8 Transmitter Enable
.ILIE EQU $10 Idle Line Interrupt Enable
.RIE EQU $20 Receive Interrupt Enable
.TCIE EQU $40 Transmision Complete Interrupt Enable
.TIE EQU $80 Transmission Interrupt Enable
SCSR EQU $10 SCI Status Register
FE EQU 1 Framing Error
NF EQU 2 Noise Flag
OR EQU 3 Overrun Error
IDLE EQU 4 1 = Idle Line Detected
RDRF EQU 5 Receive Data Register Full
TC EQU 6 Transmission Complete
TDRE EQU 7 Transmit Data Register Empty
.FE EQU 2 Framing Error
.NF EQU 4 Noise Flag
.OR EQU 8 Overrun Error
.IDLE EQU $10 1 = Idle Line Detected
.RDRF EQU $20 Receive Data Register Full
.TC EQU $40 Transmission Complete
.TDRE EQU $80 Transmit Data Register Empty
SCDR EQU $11 SCI Data Register
PAGE
* Timer Registers
TCR EQU $12 Timer Control Register
OLVL EQU 0 Output Level
IEDG EQU 1 Input Edge
TOIE EQU 5 Timer Output Interrupt Enable
OCIE EQU 6 Output Compare Interrupt Enable
ICIE EQU 7 Input Capture Interrupt Enable
.OLVL EQU 1 Output Level
.IEDG EQU 2 Input Edge
.TOIE EQU $20 Timer Output Interrupt Enable
.OCIE EQU $40 Output Compare Interrupt Enable
.ICIE EQU $80 Input Capture Interrupt Enable
TSR EQU $13 Timer Status Register
TOF EQU 5 Timer Overflow Flag
OCF EQU 6 Output Compare Flag
ICF EQU 7 Input Capture Flag
.TOF EQU $20 Timer Overflow Flag
.OCF EQU $40 Output Compare Flag
.ICF EQU $80 Input Capture Flag
ICRH EQU $14 Input Capture Register High
ICRL EQU $15 Input Capture Register Low
OCRH EQU $16 Output Compare Register High
OCRL EQU $17 Output Compare Register Low
TCTRH EQU $18 Counter Register High
TCTRL EQU $19 Counter Register Low
ATCTRH EQU $1A Alternate Counter Register High
ATCTRL EQU $1B Alternate Counter Register Low
* end of C4C8REG.S